Overview
Scan-based testing has been widely adopted in digital circuits as it has been proven to be a cost-effective method to achieve good test coverage. Scan elements and clocking may occupy nearly 30% of a chip area. It has been reported that 10-30% detected defects can cause scan chains to fail. As the silicon area occupied by scan chains and their control logic is still increasing and circuit components is continuously shrinking in size, it has become increasingly important to identify which scan cell on a faulty scan chain is defective.
The scan chain diagnosis techniques may be classified into three main categories: tester-based, hardware-based, and software-based diagnosis techniques. Tester-based diagnosis techniques use a tester to control scan chain shift operations. Physical failure analysis (PFA) equipments are sometimes used together with a tester to observe defective responses at different locations and to identify a failing scan cell. These techniques normally provide very good diagnosis resolution. However, they are difficult to apply to chips with embedded compression circuits without resorting bypass mode. It is also difficult to apply these techniques in volume diagnosis environment. Hardware-based methods use specially-designed scan chains and scan cells to facilitate the diagnosis process. These methods are effective in isolating scan chain defects. However, the requirement of extra hardware, the specially-designed scan chains/cells, may not be acceptable in many product designs. Software-based techniques use algorithmic diagnosis procedures to identify failing scan cells. It may run chain diagnosis with conventional scan chains with or without embedded compressions.
The software-based chain diagnosis techniques may be further classified into three categories: model-based, data-driven, and hybrid techniques. In model-based chain diagnosis, fault models and pattern simulation are employed. In data-driven chain diagnosis, signal profiling, filtering and edge detections are applied. These two approaches can be combined to form the hybrid chain diagnosis techniques. For example, the reference of Y. Huang et al., “Scan chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG,” Proc. Asian Test Symp., 2009, pp. 35-40, which is incorporated herein by reference, discusses applying both model-based simulation of masked scan patterns and statistical analysis of unloading test response data. Details about these three categories are provided below.
Terminologies
Test patterns used in chain diagnosis are often classified into 3 categories: chain patterns, scan patterns, and special chain diagnostic patterns.
A chain pattern (or chain flush pattern) is a test pattern that is used only in shift-in (loading) and shift-out (unloading) processes without pulsing capture clocks during a test. As such, test data of a chain pattern loaded to scan chains are isolated from the functional logic of a circuit under test. By applying chain patterns, scan chain integrity can be tested and faulty scan chains (or defective scan chains) and fault models may be identified.
A scan pattern is a test pattern that is used in shift-in, launch, capture, and shift-out processes. Scan patterns are also referred to as ATPG (Automatic Test Pattern Generation) scan patterns or scan ATPG patterns. Scan patterns are usually used to test and diagnose the functional logic during manufacturing tests. They can also be used in chain test and diagnosis.
A special chain diagnostic pattern is a test pattern generated only for scan chain diagnosis purpose. Special chain diagnostic patterns may include special functional patterns and random patterns generated on-line by a tester (test equipment).
To describe a chain diagnosis method, typically each scan cell in a scan chain is given an index. Without losing generality, the cell connected to scan-output is numbered 0 and the cells in the chain are numbered incrementally from scan-output to scan-input. The scan cells between the scan chain input and the scan input terminal of a scan cell are called the “upstream cells” of the scan cell, while the scan cells between the scan chain output and the scan output terminal of a scan cell are called the “downstream cells” of the scan cell.
Scan chain fault models may be classified into nine categories: slow-to-rise, slow-to-fall, slow, fast-to-rise, fast-to-fall, fast, stuck-at-0, stuck-at-1, and indeterminate faults. Faults in the first three categories are normally caused by setup-time violations while those in the next three categories are normally caused by hold-time violations. With a specific fault model, a scan chain defect can also be modeled as a permanent fault (the fault that happens for all shift cycles) or an intermittent fault (the fault that happens only for a subset of shift cycles). Note that the defect itself is still permanent, but the fault model used to represent the defect is intermittent. For example, an intermittent stuck-at-0 fault refers to a defect that can cause some shift operations to fail as if a stuck-at-0 fault intermittently appears while which shift cycles may fail is not known.
The “noise” is defined as any discrepancy between the real defect behavior and the defect behavior given by a software-based diagnosis system. The sources of the noise include, but not limited to:
(1) discrepancy between a fault model and un-modeled realistic defects,
(2) defects that may impact both scan chains, control logic and/or clock systems,
(3) errors that are introduced into the failure log, during the failure log's generation/translation/ATE (automatic test equipment) truncation processes,
(4) imperfectness/bugs of simulation procedures in EDA (electronic design automation) tools, and
(5) unrepeatable test results due to transient effects/testing environment changes.
Model-Based Chain Diagnosis
A model-based chain diagnosis method first identifies faulty scan chains and the corresponding fault models by using chain patterns. Fault simulations are then performed. A fault is algorithmically “injected” to one scan cell on a faulty chain. The loaded values of the downstream cells are accordingly modified for all scan patterns. For example, suppose a scan pattern has good machine loaded value 001110011010 on the faulty chain. If a permanent stuck-at-1 fault is injected on scan cell 8 of this chain, the loaded values will be modified as 001111111111. After pulsing the capture clock, the simulated captured values in the upstream of the failing scan cell on this chain will also be modified. For example if the simulated captured value is 101011101011, the unloaded values will be 111111101011. The fault simulation is performed one cell at a time. The simulation results are compared with the results observed on the tester (ATE). The cell(s) that matches the best are reported as suspect(s).
The advantages of the fault model and simulation based algorithm include (1) applicability of manufacturing ATPG scan patterns, (2) direct diagnosis without resorting to bypass mode in the case of embedded compression, and (3) good diagnosis resolution and accuracy when the defect can be modeled as permanent faults. The disadvantages include (1) poor diagnosis resolution for intermittent faults and (2) diagnosis results susceptible to noise interference.
Data-Driven Chain Diagnosis
A data-driven chain diagnosis method often uses special chain diagnosis patterns. These patterns could be either functional test patterns that start from an initial state, or scan patterns that start with all “0”s or all “1”s. The purpose of using such patterns is to avoid (or minimize) any faulty values introduced with the loading of scan chains. Therefore, all (or most) of the failing bits are caused in the process of unloading scan chains. Then the diagnosis can be performed by monitoring from which scan cell the signal probability has been significantly changed. These algorithms select scan patterns to randomize signal probability of scan cells before unloading. The failing scan cell position can be identified by comparing the observed signal profile on a tester and the expected signal profile.
The advantages of the data-driven algorithm include (1) good diagnosis accuracy even if the realistic defect's behavior is difficult to model, (2) no requirement of design information, (3) tolerance to noises, and (4) fast diagnosis speed because it does not rely on pattern simulations for each cell of a faulty scan chain. The disadvantages include: (1) Manufacturing ATPG scan patterns cannot be used because the faulty values during scan chain loading procedures could be propagated to the faulty chain itself which would compromise signal profiling results; and (2) it cannot apply to circuits with embedded compression logic without using bypass mode.
Hybrid Chain Diagnosis
As noted previously, a hybrid approach combines model-based techniques and data-driven techniques. The combination allows manufacturing ATPG scan patterns to be utilized for chain diagnosis. Manufacturing ATPG scan patterns are preferred in a practical chain diagnosis application because these scan patterns usually generated for testing circuits during manufacturing processes are readily available. If the diagnosis result from applying manufacturing ATPG scan patterns is not satisfactory, additional diagnostic patterns may be created.
The hybrid chain diagnosis approach often uses masking techniques to avoid or minimize any faulty values introduced during loading scan patterns to scan chains. One of the masking techniques is the X-masking technique. This technique identifies sensitive loading bits for each scan pattern and replaces each of them with an “X”. A sensitive loading bit of a test pattern corresponds to a scan cell of which a loaded value can be different from the good-machine loaded value due to a defect or defects existing in the scan chain. For different fault models, the sensitive loading bits may be different. For example, suppose a scan pattern has a good machine loaded value 001110011010 on the faulty chain. If a stuck-at-1 fault is identified, all “0”s are sensitive loading bits. The X-masking technique will replace “0”s with “X”s and thus the loaded value will become XX111XX11X1X. If a fast-to-rise fault is identified instead, all “0”s within the “10” transitions will become sensitive loading bits, and the loaded value will be changed to “00111X011X1X”.
Once scan patterns are X-masked, simulations may be performed to derive expected unloading values. Based on the expected unloading values and the observed unloading values (test response data collected after applying the scan patterns), failing probabilities for scan cells in a faulty scan chain are calculated and failing scan cells may be identified.
The hybrid chain diagnosis techniques and the data-driven chain diagnosis techniques together are referred to as profiling-based chain diagnosis techniques.